Until two decades ago, the design of digital integrated circuits and systems was a major challenge as speed and transistor density did not match the processing requirements of many algorithms and computing systems. However, for the last two decades, the rapid progress in technology alleviated this bottleneck significantly, allowing designers to implement even complex systems and algorithms with ease, often by simply waiting for the next process node. Unfortunately, with the end of technology scaling in-sight, this "Happy Scaling Era" reaches its end and innovations in low-complexity algorithms and efficient dedicated integrated circuits are in greater demand than ever.
In this talk, I will discuss some of the major challenges ahead together with the associated trends in application requirements and describe some promising areas of innovation. In particular, I will discuss how memory requirements dominate power, performance, and energy of integrated circuits and why circuit innovation alone is often insufficient for meeting processing requirements of emerging applications. I will argue that joint consideration of circuits and algorithms can lead to new and innovative solutions, approaching the task from a side that is quite different from the techniques applied in the 1990s when designers were facing similar challenges. I will also point out and discuss associated new approaches in circuit design which rely on state-of-the-art technologies and their features.
Andreas Burg received his Diploma and his PhD degrees in 2000 and in 2006, respectively, both from the ETH Zurich. After his PhD, he co-founded Celestrius, a fabless semiconductor company in the area of circuits and systems for wireless communications. After two years as SNF Assistant Professor at ETH Zurich from 2009-2010, he joined the EPFL, where he is an Associate Professor since June 2018, heading the Telecommunications Circuits Lab. His research interests are in VLSI circuits and systems, in VLSI signal processing and in Communications. He is a member of IEEE and contributes actively to conferences and journals. In his career, he was involved in the tapeout of more than 40 ASICs and he published more than 250 papers.
The Internet of Things (IoT) has been hailed as the next frontier of innovation in which our everyday objects are connected in ways that improve our lives and transform industries. The IoT concept is poised to reach more than 20 billion connected devices by 2025, but major key challenges remain in achieving this potential due to inherent resource-constrained nature of IoT systems, coupled with the computing power and data gathering requirements of Big Data applications, which can result in degraded and unreliable behavior of IoT nodes, or a global energy crisis when IoT is fully deployed in the future. In this keynote, Prof. Atienza will first discuss the challenges of ultra-low power (ULP) design and communication in IoT nodes for Big Data analytics. Then, the opportunities for edge computing in next-generation smart IoT nodes will be highlighted as a scalable way to fully deliver the IoT concept. This new trend of smarter electronics architectures will need to combine new ULP multi-core embedded systems with neural network accelerators, as well as including energy-scalable software layers, to gracefully adapt the energy consumption and precision of the IoT application outputs according to the requirements of our surrounding world and available energy at each moment in time, as living organisms do to operate efficiently in the real world.
David Atienza is Associate Professor of Electrical and Computer Engineering and leads the Embedded Systems Laboratory (ESL) at EPFL, Switzerland. He received his MSc and PhD degrees in Computer Science and Engineering from UCM (Spain) and IMEC (Belgium). His research interests focus on system-level design methodologies for energy-efficient multi-processor system-on-chip architectures (MPSoC) and next-generation smart embedded systems (particularly wearables) for the Internet of Things (IoT) era. In these fields, he is co-author of more than 250 publications, seven patents, and received several best paper awards in top conferences. He also was the Technical Program Chair of DATE 2015 and General Chair of DATE 2017. Dr. Atienza has received the DAC Under-40 Innovators Award in 2018, IEEE TCCPS Mid-Career Award in 2018, an ERC Consolidator Grant in 2016, the IEEE CEDA Early Career Award in 2013, the ACM SIGDA Outstanding New Faculty Award in 2012, and a Faculty Award from Sun Labs at Oracle in 2011. He is an IEEE Fellow and an ACM Distinguished Member.
Connected devices such as Internet of Things (IoT) and wireless sensing systems are becoming widespread for their various sensing, processing and automation capabilities. Power conversion efficiency in radio frequency (RF) remotely powered systems is strictly important for operational power and distance requirements. This talk will discuss power conversion techniques for Radio Frequency Identification (RFID) systems as well as remotely powered and battery-less integrated systems; such as biomedical devices in wearable and implantable applications. In this context, fundamental blocks of remotely powered systems, which consist of remote powering front-end (rectifier), wireless communication, power supervisory, and data acquisition circuitry, will be presented. Methods and design trade-offs on rectifiers with different circuit techniques such as self-threshold cancellation, active switches, etc. will be elaborated with the emphasis on power conversion efficiency.
Onur Kazanc received his B.Sc. degree in Electrical and Electronics Engineering in 2008 from Yeditepe University in Istanbul, Turkey. He received his M.Sc. and Ph.D. degrees in Microelectronics from Swiss Federal Institute of Technology in Lausanne (EPFL) in 2010 and 2014, respectively. His research had focused on far-field remotely powered sensor systems for real-time monitoring with the emphasis on wearable and implantable biomedical applications. He worked on the development of wireless integrated sensor platform operating at 2.45 GHz. He continued his research as a post-doctoral researcher at EPFL on the development of energy harvesting, power management and wireless communication systems of wearable applications until 2015. Since then, he works as a Senior Design Engineer at ON Semiconductor Switzerland on the development of medical and wireless integrated systems. His research interests include RF front-end design of remotely powered wireless sensor systems and wireless charging applications.